Design process of the MASH 2-2 sigma-delta modulator

This paper presents the design process of the cascaded (MASH) 2-2 sigma-delta modulator. For this purpose, several sigma-delta modulator topologies were studied at the system and schematic levels. Simulation at the system level was used to define the requirements for the operational transconductance amplifier (OTA), which is a part of the integrator. Sigma-delta modulators were designed using a 0.18 µm CMOS technology library. The influence of temperature swing, process variations and noise on the characteristics of second-order sigma-delta modulators was taken into account during simulation. As a result of the simulation, the optimal second-order topology was selected. This topology was used to design the cascaded (MASH) 2-2 sigma-delta modulator. The developed modulator has a resolution of 15.97 effective bits, a working frequency band of 20 kHz, consumes 12 mW of power at a supply voltage of 3.3 V. The occupied area of the circuit on the chip is 0.22 mm2. A device with such characteristics can be used in interfaces of micromechanical sensors.