A pipeline analog-to-digital converter in 180 nm CMOS

A pipelined analog-to-digital converter (ADC) is presented, which was designed using 180 nm complementary metal-oxide semiconductor (CMOS) technology with a supply voltage of 1.8 V from Micron JSC. The ADC circuit consists of a sample-and-hold device, an 8-level redundant stage, five 6-level redundant pipeline stages, a back-end 3-bit ADC, as well as synchronization circuits, an adder and multiplexers to get at the output the 16-bit direct binary code of the whole ADC or the redundant code from first to fifth stages. The pipeline is implemented as a switched-capacitor circuit using operational transconductance amplifiers. The simulation of the ADC in the time domain in the Virtuoso analog design environment from Cadence DS was performed. The clock frequency was set to 50 MHz. The power consumption was about 52 mW, the following main characteristics were achieved: SINAD = 74.6 dB
(ENOB = 12 bits) and SFDR = 75.3 dB.