Incremental delta-sigma modulator

A delta-sigma modulator with reset for incremental ∆Σ ADCs for the 180 nm CMOS technology with a supply voltage of 3.3 V from Mikron JSC is presented. The simulation of the ∆Σ modulator in the time domain in the Virtuoso analog design environment from Cadence DS was performed. The clock frequency was set to 6.25 MHz. The power consumption was about 9.5 mW. The reset was performed every 32 or 128 clock cycles. The results of the ∆Σ modulator simulation were processed in MATLAB. The digital decimation filter in the form of a cascade of integrators was realized in software. At the oversampling ratio of 32, the modulator shows SINAD = 69.3 dB (ENOB = 11.2 bits) and SFDR = 76.9 dB. At the oversampling ratio of 128, SINAD = 88.7 dB (ENOB = 14.4 bits) and SFDR = 92.7 dB are achieved. The crystal dimensions were 640×340 µm. The ∆Σ modulator circuit is suitable for precise digitization of sensor signals in the audio frequency range.