MASH 2-2 Delta-Sigma Modulator with Dynamic Element Matching in 0.18 µm CMOS Technology

Circuits and Systems for Receiving, Transmitting and Signal Processing

Design details and results of post-layout simulation for multi-stage noise-shaping 2-2 delta-sigma modulator based on 0.18 µm CMOS from JSC Mikron are presented. The circuit consists of two similar 2nd order stages connected sequentially and based on fully differential operational transconductance amplifiers and switched capacitors. The delta-sigma modulator processes a differential input signal and has a two-bit quantizer, which is a simple 2-bit analog-to-digital converter that contains three differential comparators. A special digital circuit is used, which provides dynamic element matching, also known as dynamic weighted averaging in digital-to-analog converter, which is connected to the switched capacitors. Supply voltage is 1.8V. Clock frequency is 1 MHz. Frequency band of the input signal is up to 8 kHz. Dynamic range is 62 dB. Power consumption is 1.9 mW.