Reduced voltage stress Class E power amplifier operating a complex impedance load: A performance analysis

Circuits and Systems for Receiving, Transmitting and Signal Processing
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Abstract:

Class E power amplifiers (PAs) attract the interest of experts involved in the development of communication and telecommunications equipment due to their high efficiency. However, the high voltage stress across transistors, which exceeds the supply voltage by 3.6−4 times, limits the output power of such amplifiers. An alternative to solve this issue could be a PA in which the peak voltage across transistor is reduced by 2 times, but still maintains the main advantages of traditional Class E, such as zero-voltage switching (ZVS) and zero-derivative voltage switching (ZDVS). In well-known publications, the study of the characteristics of PAs with lower voltage across transistors is limited to the particular case of a real impedance load. However, this condition may not be true when the PA operates in a frequency band, which will inevitably lead to errors in calculating their characteristics. The objective of the paper is to develop an analytical model of Class E PA with reduced voltage stress when operating with complex impedance load. The adequacy of the analytical model is confirmed by simulation, which shows that the relative error in the calculation of the main characteristics of the PA does not exceed 6.5%. The issues of synthesizing a filtering and matching circuit have been considered that ensures expansion of the frequency band at specified rated values in output power and voltage stress in transistor turned-on moment.