CMOS inductor design features for LTE devices

Circuits and Systems for Receiving, Transmitting and Signal Processing

This work is devoted to some aspects of the development of planar elements of the microwave path, which are used in the design of low-noise LTE range amplifiers, namely inductors, for further employment as part of the NB-IoT transceiver. General theoretical calculations on the design of high-frequency inductors are given. By the example of a multilayer CMOS 90 nm inductor with a nominal value of 7 nH, we demonstrated the influence of the structure thickness obtained by replicating layers used to get the required skin layer thickness and to achieve the best quality factor in the LTE frequency range from 0.5 to 3.5 GHz by means of electromagnetic (EM) models. For a better understanding of the inductor operation, the models obtained as a result of the EM simulation for different values of the substrate conductivity are compared. The obtained data partially refute the need of increasing the maximum thickness of the inductors by a set of upper metals combined using multiple TSV arrays for silicon process stacks. Due to the increasing of the capacitive influence of the substrate on the lower metal layers of the inductor, the highest values of Q-factor and self-resonance frequencies are achieved by the structures with a minimum number of metal layers, despite the negative influence of the skin effect for low frequencies.