This paper shows the advantages of using graphical programming in LabVIEW to design a model of an electronic device with adjustable parameters. The model of the digital gain error calibration and correction system for a 12-bit 200-Ms/s pipelined ADC has been constructed. The results of computer simulation in LabWIEV are presented. As shown, digital error correction can reduce op-amp requirements while maintaining the same SNDR and SFDR ratios. For example, the simulation has shown that operational amplifiers with a DC gain of 48 dB instead of 68 dB can be used in a pipelined ADC with digital correction. This approach can reduce ADC power twofold.