Spiking neural network analog two-variable neuron implementation

Intelligent Systems and Technologies, Artificial Intelligence
Authors:
Abstract:

Currently, the problem of using neural networks in embedded systems, which have constraints on power consumption and area occupied, is relevant. At the same time, there is growing interest in spiking neural networks — more biologically realistic neural networks with potentially higher energy efficiency. This paper presents a review of existing hardware implementations of spiking neural networks, implemented both in the digital and analog domains. A hardware implementation of analog spiking neuron and synapse fabricated in Mikron JSC 180 nm CMOS technology with a reduced supply voltage of 0.6 V is presented. According to the simulation results, the energy consumption of a single neuron was 1.46 pJ/spike. The paper also provides a formula for comparing energy consumption between neurons fabricated in different technologies and with different supply voltages. According to this formula, the energy consumption of the implemented neuron is comparable to that of the referenced sources.

  • References

    1. Barnwal R., Srivastava R., Vimalathithan R., Kala S. Advanced Driver Assistance System for Autonomous Vehicles Using Deep Neural Network. 2022 IEEE 10th Region 10 Humanitarian Technology Conference (R10-HTC), 2022, Pp. 342–347. DOI: 10.1109/R10-HTC54060.2022.9929654

    2. Zhang M., Liao W., Zhang J., Gao H., Wang F., Lin B. Embedded Face Recognition System Based on Multi-task Convolutional Neural Network and LBP Features. 2019 IEEE International Conference of Intel-ligent Applied Systems on Engineering (ICIASE), 2019, Pp. 132–135. DOI: 10.1109/ICIASE45644.2019.9074-104

    3. Zhao Y., Yang C., Wang Y., Cai J., Xue Y. Face Recognition for Embedded System Based on Optimi-zed Triplet Loss Neural Network. 2020 3rd International Conference on Advanced Electronic Materials, Compu-ters and Software Engineering (AEMCSE), 2020, Pp. 260–263. DOI: 10.1109/AEMCSE50948.2020.00063

    4. Bahnsen F.H., Kaiser J., Fey G. Designing Recurrent Neural Networks for Monitoring Embedded Devices. 2021 IEEE European Test Symposium (ETS), 2021, Pp. 1–4. DOI: 10.1109/ETS50041.2021.9465460

    5. Chen L., Xiong X., Liu J. A Survey of Intelligent Chip Design Research Based on Spiking Neural Networks. IEEE Access, 2022, Vol. 10, Pp. 89663–89686. DOI: 10.1109/ACCESS.2022.3200454

    6. Zhang M., Gu Z., Pan G. A Survey of Neuromorphic Computing Based on Spiking Neural Networks. Chinese Journal of Electronics, 2018, Vol. 27, No. 4, Pp. 667–674. DOI: 10.1049/cje.2018.05.006

    7. Shinde R.K., Shinde K.D., Mane P.B., Mehta H. Bio-Inspired Spiking Neural Networks for Real-Time Biomedical Signal Processing. 2025 International Conference on Information, Implementation, and Innovation in Technology (I2ITCON), 2025, Pp. 1–5. DOI: 10.1109/I2ITCON65200.2025.11208866

    8. Chen Y.-N., Chen Y.-H. Real-Time ECG Recognition Using Convolutional Spiking Neural Networks with Sparse Encoding for Arrhythmia Detection. 2025 IEEE 14th Global Conference on Consumer Electronics (GCCE), 2025, Pp. 380–381. DOI: 10.1109/GCCE65946.2025.11275376

    9. SalimiKia A., Mozaffari S., Ahmadi M., Alirezaee S. Energy-Efficient Spike Encoding for Implemen-ting Spiking Neural Networks on FPGA. 2025 IEEE Canadian Conference on Electrical and Computer Engi-neering (CCECE), 2025, Pp. 502–506. DOI: 10.1109/CCECE64018.2025.11364354

    10. Deeksha, Krishnan A., Chandrachoodan N., Nambiar M. Low-Power FPGA Implementation of Spi-king Neural Networks with Optimized Event-Based Encoding. 2025 IEEE 7th International Conference on Emerging Electronics (ICEE), 2025, Pp. 1–4. DOI: 10.1109/ICEE67165.2025.11409777

    11. Chu H., Yan Y., Gan L., Jia H., Qian L., Huan Y. A Neuromorphic Processing System with Spike-Dri-ven SNN Processor for Wearable ECG Classification. IEEE Transactions on Biomedical Circuits and Systems, 2022, Vol. 16, No. 4, Pp. 511–523. DOI: 10.1109/TBCAS.2022.3189364

    12. Davies M., Srinivasa N., Lin T.-H., Chinya G., Cao Y., Choday S.H. Loihi: A Neuromorphic Manycore Processor with On-Chip Learning. IEEE Micro, 2018, Vol. 38, No. 1, Pp. 82–99. DOI: 10.1109/MM.2018.112130359

    13. Ochs M., Dietl M., Brederlow R. A Circuit Concept for Energy-Efficient Spiking Neural Network Systems with a FOM of 86.9fJ/SOP. 2024 IEEE Biomedical Circuits and Systems Conference (BioCAS), 2024, Pp. 1–5. DOI: 10.1109/BioCAS61083.2024.10798224

    14. Polidori E., Camisa G., Mesri A., Ferrari G., Polidori C., Mastella M. Experimental validation of an analog spiking neural network with STDP learning rule in CMOS technology. 2022 IEEE International Conference on Metrology for Extended Reality, Artificial Intelligence and Neural Engineering (MetroXRAINE), 2022, Pp. 187–192. DOI: 10.1109/MetroXRAINE54828.2022.9967583

    15. Moriya S., Yamamoto H., Sato S., Yuminaka Y., Horio Y., Madrenas J. A Fully Analog CMOS Imple-mentation of a Two-variable Spiking Neuron in the Subthreshold Region and its Network Operation. 2022 In-ternational Joint Conference on Neural Networks (IJCNN), 2022, Pp. 1–7. DOI: 10.1109/IJCNN55064.2022.9891920

This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License
Next article