Linearization of the Analog-to-Digital Converter for an FPGA-based Direct Digital Receiver

The goal of this work is to provide linearization of the analog-to-digital converter for an FPGA-based Direct Digital Receiver. One of the techniques for implementing that is the LUT-based calibration and correction technique inside the FPGA, which was used for obtaining better characteristics of SNDR, SFDR and INL of the FPGA-based parametrized 14-bit model of pipelined ADC. The experimental part consists of the implementation of the FPGA-based parametrized 14-bit model pipelined ADC using MATLAB/Simulink. Its calibration and LUT-based correction were performed using both MATLAB/Simulink and FPGA. The DDS generator was implemented inside the FPGA. Code was written in Verilog HDL. The values of the dynamic characteristics of the ADC (SNDR and SFDR) were obtained before and after calibration, and compared. The influence of the DC gain and that of the capacitors of the MDAC was taken into account and observed. The influence of changes in the DC gain and capacitor mismatch of MDAC inside the stage was also taken into account for both SNDR and SFDR, as well as for the static characteristic, INL, which was also observed.

Citation: Krneta M., Piatak I.M. Linearization of the Analog-to-Digital Converter for an FPGA-based Direct Digital Receiver. St. Petersburg State Polytechnical University Journal. Computer Science. Telecommunications and Control Systems. 2017, Vol. 10, No. 3, Pp. 44–52. DOI: 10.18721/JCSTCS.10304