Synthesis of decimating filter for delta-sigma analog-to-digital converter

The paper discusses questions of synthesis of decimating filter with optimal cascade sequence and low power consumption for delta-sigma analog-to-digital converter (ADC). The proposed filter has a passband of 1 MHz and stopband attenuation of more than 60,8 dB, ADC's dynamic range is 58,4 dB, this accord to dynamic range of 10 bit ADC. The estimated power consumption of the proposed decimating filter is 4 mW assuming realization with CMOS technology 0,18 urn.