Computing, Telecommunication and Control Информатика, телекоммуникации и управление 2687-0517 6 10.18721/JCSTCS.19206 A spiking neural network in 180 nm CMOS Импульсная нейронная сеть по технологии КМОП 180 нм Pilipko M.M. m_m_pilipko@rambler.ru Morozov Dmitriy dvmorozov@inbox.ru 30 06 2026 19 2 61 69

A hardware implementation of a spiking neural network for classifying font images of letters and numbers has been developed in the 180 nm CMOS technology of Mikron JSC. The layout dimensions are 500 × 550 µm. The supply voltage is 1.0 V. The average power consumption is approximately 0.06 mW. The clock frequency is up to 10 MHz. The neural network contains four layers of 15, 8, 8, and 10 nodes, respectively. The input data and synapse weights have a bit width of 3 bits. A comparison with the results from other studies is performed.

 CMOS analog neural network leaky integrating neuron References Asghar M.S., Arslan S., Kim H.W. Low Power Spiking Neural Network Circuit with Compact Synapse and Neuron Cells. 2020 International SoC Design Conference (ISOCC), 2020, Pp. 157–158. DOI: 10.1109/ISOCC50952.2020.9333105 Asghar M.S., Arslan S., Kim H.W. A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits. Sensors, 2021, Vol. 21, No. 13, Art. no. 4462. DOI: 10.3390/s21134462 Skrebenkov D.I., Budanov D.O. Hardware Implementation of Neural Networks. 2024 International Conference on Electrical Engineering and Photonics (EExPolytech), 2024, Pp. 99–102. DOI: 10.1109/EEx-Polytech62224.2024.10755531 Skrebenkov D.I., Budanov D.O. Methods for Reducing Power Consumption in Hardware Implemen-ted Neural Networks. 2025 International Conference on Electrical Engineering and Photonics (EExPolytech), 2025, Pp. 1–4. DOI: 10.1109/EExPolytech66949.2025.11252131 Mavrin I.A., Ryndin E.A., Andreeva N.V. Razrabotka analogovoi impul'snoi neironnoi seti [Development of an analog pulse neural network]. XI Nauchno-prakticheskaia konferentsiia s mezhdunarodnym uchastiem “Nauka nastoiashchego i budushchego” dlia studentov, aspirantov i molodykh uchenykh [XI Scientific and Practical Conference with International Participation “Science of the Present and Future” for students, postgra-duates and young scientists], 2023, Vol. 1, Pp. 114–118. Udovichenko V., Krokhmanskii V., Ryndin E.A. Topologiia iskusstvennogo sinapsa dlia avtomatizirovannogo proektirovaniia neironnykh setei [Artificial synapse topology for automated design of neural networks], Available: https://events.priem.etu.ru/api/open/nnb/stand-file?id=85844 (Accessed 24.06.2026) Ryndin E.A., Andreeva N.V. Integral electronic CMOS synapse. Russian Federation Patent, No. RU 2808951 C1 (2023). Ryndin E.A., Andreeva N.V. Integrated electronic synaptic CMOS element. Russian Federation Patent, No. RU 2836650 C1 (2024).