Computing, Telecommunication and Control Информатика, телекоммуникации и управление 2687-0517 10 10.18721/JCSTCS.19310 Application of asynchronous data bypass to increase performance of in-order superscalar RISC-V processor core Использование асинхронной пересылки данных для увеличения производительности суперскалярного RISC-V процессорного ядра с исполнением команд в прямой очередности Usoltsev Mikhail usol.91@mail.ru Borisovskii Fedor feka09@gmail.com Budanov Dmitriy dmitriy.budanov@gmail.com 30 09 2026 19 3 121 129

RISC-V is an open-source architecture that does not require license fees from pro-cessor core vendors. This allowed RISC-V to become widely distributed first in the micro-controller-class processor core market and subsequently in the market of higher-performance devices. Currently RISC-V processor cores with in-order execution, which combine mid-range performance, compactness, and energy efficiency are attracting the most interest from customers. This makes the task of continuing to improve them a highly relevant. This paper explores the application of a microarchitectural modification, asynchronous data bypass, to increase the performance of in-order superscalar RISC-V processor core. Asynchronous data bypass has been made for two pairs of functional blocks: between arithmetic-logic unit (ALU) and ALU, between ALU and branch unit. The main obstacle of implementing asynchronous data bypass is the creation of an extremely long logical path, which leads to violations of timing constraints. To overcome this obstacle, an approach was proposed that involves completely excluding a subset of instructions from asynchronous bypass and separating the logic of the remaining instructions into groups based on the length of the logical path. This approach made it possible to keep the logical path of asynchronous bypass no longer than the longest path of a single execution unit. The results showed that the use of asynchronous bypass can significantly increase the performance of in-order superscalar processor core. At the same time, the area overhead is very low.

 processor core superscalarity in-order asynchronous data bypass logical path References Chaver D., Harris S., Pinuel L., Kindgren O., Kakakhel Z., Owen C. The RISC-V FPGA (RVfpga) Teaching Package. IEEE Access, 2026, Vol. 14, Pp. 18455–18475. DOI: 10.1109/ACCESS.2026.3658743 Sharma M., Bhatnagar E., Puri K., Mitra A., Agarwal J. A survey of RISC-V CPU for IoT applicati-ons. Proceedings of the International Conference on Innovative Computing & Communication (ICICC), 2022, Pp. 1–4. DOI: 10.2139/ssrn.4033491 Hassan Q.F., Sagahyroon A. RISC-V: A comprehensive overview of an emerging ISA for the AI-IoT era. In: Advances in the Internet of Things (ed. Q.F. Hassan), 2025, Pp. 244–284. DOI: 10.1201/978100350-6638-15 Liu Y., Ye K., Xu C.Z. Performance evaluation of various RISC processor systems: A case study on ARM, MIPS and RISC-V. Cloud Computing – CLOUD 2021, 2022, Vol. 12989, Pp. 61–74. DOI: 10.1007/978-3-030-96326-2_5 Gao J., Zhang J. Research and Design of RISC-V Four-Stage Out-of-Order Execution Processor. 2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), 2022, Pp. 1–3. DOI: 10.1109/ICSICT55466.2022.9963329 Fu Z., Tedeschi R., Ottavi G., Wistoff N., Fuguet C., Rossi D., Benini L. Ramping up open-source RISC-V cores: Assessing the energy efficiency of superscalar, out-of-order execution. Proceedings of the 22nd ACM International Conference on Computing Frontiers, 2025, Pp. 12–20. DOI: 10.1145/3719276.3725186 Chatzopoulos O., Papadimitriou G., Wong W.S., Gizopoulos D. Energy Efficiency of Out-of-Order CPUs: Comparative Study and Microarchitectural Hotspot Characterization of RISC-V Designs. 2023 IEEE International Symposium on Workload Characterization (IISWC), 2023, Pp. 216–220. DOI: 10.1109/IISWC59245.2023.00032 Cui E., Li T., Wei Q. RISC-V Instruction Set Architecture Extensions: A Survey. IEEE Access, 2023, Vol. 11, Pp. 24696–24711. DOI: 10.1109/ACCESS.2023.3246491 Schiavone P.D., Conti F., Rossi D., Gautschi M., Pullini A., Flamand E. Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications. 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2017, Pp. 1–8. DOI: 10.1109/PATMOS.2017.8106976 Wheeler B. WD Rolls Its Own RISC-V Core: Western Digital Opens Superscalar Swerv CPU Source to Others. The Linley Group: Microprocessor Report, 2019, Pp. 1–3. [online] Available: https://documents.westerndigital.com/content/dam/doc-library/en_us/assets/public/western-digital/collateral/analyst-report/WD_Rolls_Its_Own_RISC-V_Core.pdf Western Digital. RISC-V and Open Source Hardware Address New Compute Requirements. [online] https://documents.westerndigital.com/content/dam/doc-library/en_us/assets/public/western-digital/collateral/tech-brief/tech-brief-western-digital-risc-v.pdf (Accessed 28.07.2026) Petrisko D., Gilani F., Wyse M., Jung D.C., Davidson S., Gao P. BlackParrot: An Agile Open-Source RISC-V Multicore for Accelerator SoCs. IEEE Micro, 2020, Vol. 40, No. 4, Pp. 93–102. DOI: 10.1109/MM.2020.2996145 Gonzalez A., Zhao J., Korpan B., Genc H., Schmidt C., Wright J. et al. A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET. ESSCIRC 2021 – IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021, Pp. 259–262. DOI: 10.1109/ESSCIRC53450.2021.9567768 Numan Ince M., Ledet J., Gunay M. Building An Open Source Linux Computing System On RISC-V. 2019 1st International Informatics and Software Engineering Conference (UBMYK), 2019, Pp. 1–4. DOI: 10.1109/UBMYK48245.2019.8965559 Gookyi D.A.N., Ryoo K. Selecting a Synthesizable RISC-V Processor Core for Low-cost Hardware Devices. Journal of Information Processing Systems, 2019, Vol. 15, No. 6, Pp. 1406–1421. DOI: 10.3745/JIPS.03.0129 Dörflinger A., Albers M., Kleinbeck B., Guan Y., Michalik H., Klink R., Blochwitz C., Nechi A., Berekovic M. A comparative survey of open-source application-class RISC-V processor implementations. Proceedings of the 18th ACM International Conference on Computing Frontiers, 2021, Pp. 12–20. DOI: 10.1145/3457388.345865 Li Y., Yu Z., Ji W. Design and Performance Optimization of a Risc-V Processor with Five-Stage Pipeline. 2025 IEEE 6th International Seminar on Artificial Intelligence, Networking and Information Technology (AINIT), 2025, Pp. 1–5. DOI: 10.1109/AINIT65432.2025.11035005 Kra Y., Shoshan Y., Rudin Y., Teman A. HAMSA-DI: A Low-Power Dual-Issue RISC-V Core Targeting Energy-Efficient Embedded Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 2024, Vol. 71, No. 1, Pp. 223–236. DOI: 10.1109/TCSI.2023.3323425