This work presents the design and analysis of a reconfigurable hardware accelerator for solving a system of linear equations using Jacobi method, implemented on a reconfigurable device, as well as a comparative study of software and hardware implementations. Recent advancements in computing capabilities have been hindered by the so-called “walls”: memory, power consumption and clock frequency limitations imposed by current technology. Solutions to overcome these “walls” include reconfigurable computing and high-level synthesis. The system under development and analysis was described in the C++ language and implemented using a high-level synthesis method, which reduces design time and enables more efficient exploration of different hardware architectures. The comparative analysis showed a performance increment over the original implementation, with energy consumption comparable to that of a modern mid-class microprocessor.